140 lines
7.4 KiB
Markdown
Executable File
140 lines
7.4 KiB
Markdown
Executable File
# BTC.sh (Build Tool Chain)
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## Version 0.4.0
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BTC.sh is a bare-metal, cleanroom toolchain generation engine designed for
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independent infrastructure. It produces hardened, microarchitecture-optimized
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cross-toolchains across 19 target configurations spanning Intel, AMD, ARM,
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MIPS, and Tilera TILE-Gx processors.
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The project treats the build process as a forensic exercise: it does not simply
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compile code — it instantiates a sovereign build environment in volatile memory,
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stamps every resulting binary with an immutable hardware identity, and monitors
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the forge's health via integrated thermal and entropy sentinels.
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## Cross-Compilation Targets
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BTC.sh 0.4.0 supports 19 targets organized into five families. Target selection is
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driven by an associative array registry — a table-driven design following PEP
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868 and MISRA conventions.
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### Intel HEDT / Server (5 targets)
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| Target ID | Microarchitecture | ISA | C Library | Description |
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|--------------------|----------------------|--------|-----------|--------------------------------------------------|
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| `haswell` | haswell | AVX2 | glibc | Intel Haswell (Core i7-4xxx / Xeon E5 v3) |
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| `haswell-ep` | haswell | AVX2 | glibc | Intel Haswell-EP X99 (Xeon E5/E7 v3) |
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| `skylake` | skylake | AVX2 | glibc | Intel Skylake (Core i7-6xxx / Xeon v5) |
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| `skylake-x` | skylake-avx512 | AVX512 | glibc | Intel Skylake-X X299 (i9-7xxx / Xeon Scalable) |
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| `skylake-server` | skylake-server | AVX512 | glibc | Intel Skylake-Server (Xeon SP 1st/2nd Gen) |
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### AMD Ryzen / EPYC (4 targets)
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| Target ID | Microarchitecture | ISA | C Library | Description |
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|-------------|--------------------|--------|-----------|------------------------------------------|
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| `znver1` | znver1 | AVX2 | glibc | AMD Zen1 (Ryzen 1000 / EPYC Naples) |
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| `znver2` | znver2 | AVX2 | glibc | AMD Zen2 (Ryzen 3000 / EPYC Rome) |
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| `znver3` | znver3 | AVX2 | glibc | AMD Zen3 (Ryzen 5000 / EPYC Milan) |
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| `znver4` | znver4 | AVX512 | glibc | AMD Zen4 (Ryzen 7000 / EPYC Genoa) |
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### AMD APU (4 targets)
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| Target ID | Microarchitecture | ISA | C Library | Description |
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|------------|--------------------|--------|-----------|-------------------------------------------------|
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| `apu-zn1` | znver1 | AVX2 | glibc | AMD APU S1 Zen — Raven Ridge (2400GE / 3200GE) |
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| `apu-zn2` | znver1 | AVX2 | glibc | AMD APU S2 Zen+ — Picasso (3250U / 3500U) |
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| `apu-zn3` | znver2 | AVX2 | glibc | AMD APU S3 Zen2 — Renoir (4500U / 4700U) |
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| `apu-zn4` | znver3 | AVX2 | glibc | AMD APU S4 Zen3 — Cezanne (5500U / 5700U) |
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### Intel Atom (4 targets)
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| Target ID | Microarchitecture | ISA | C Library | Description |
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|----------------------|--------------------|---------|-----------|------------------------------------------------------------|
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| `atom-silvermont` | silvermont | SSE4_2 | glibc | Atom Silvermont — Bay Trail (Z3000 / E38xx series) |
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| `atom-goldmont` | goldmont | SSE4_2 | glibc | Atom Goldmont — Apollo Lake (x5-Z8350 / N4200) |
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| `atom-tremont` | tremont | SSE4_2 | glibc | Atom Tremont — Elkhart Lake (x6000E series) |
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| `atom-sierraforest` | sierraforest | SSE4_2 | glibc | Atom Sierra Forest — x7000RE E-core cluster |
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### Embedded / Non-x86 (2 targets)
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| Target ID | Architecture | Microarchitecture | ISA | C Library | Description |
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|------------|--------------|--------------------|--------|-----------|-----------------------------------------------------|
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| `mipselr2` | mipsel | mips32r2 | MIPS32 | musl | MIPS32R2 LE o32 (MALTA / embedded routers) |
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| `armv7` | arm | armv7-a | NEON | musl | ARMv7-A HF NEON (Cortex-A7/A9/A15, RPi 2/3 32-bit) |
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| `tilegx` | tilegx | tilegx | TILE | musl | Tilera TILE-Gx72 (mesh VLIW) |
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## ISA Tier Architecture
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Six ISA tiers govern optimization flags. GCC is configured with
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`--with-arch=<march>` and `--with-cpu=<march>` in both Stage 1 and Stage 2 to
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ensure the cross-compiler defaults to the target microarchitecture:
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| ISA Tier | Flags |
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|----------|-----------------------------------------------------|
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| AVX512 | `-mavx512f -mavx512dq -mavx512vl -mavx512bw` |
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| AVX2 | `-mavx2` |
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| SSE4_2 | `-msse4.2` |
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| NEON | `-mfpu=neon -mfloat-abi=hard` |
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| MIPS32 | (per-target: `--with-arch=mips32r2 --with-float=soft`) |
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| TILE | (per-target: `--with-arch=tilegx`) |
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The SSE4_2 tier exists because Intel Atom and AMD APU low-power cores lack AVX
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support entirely.
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## Usage
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```bash
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# Build a cross-toolchain for a specific target
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sudo ./BTC.sh <target_id>
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# Build a host-optimized native toolchain
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sudo ./BTC.sh --native
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# List all available targets with descriptions
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sudo ./BTC.sh --list
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```
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## Architectural Pillars
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Built to LFS 13.0 stable standards (Binutils 2.46,
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GCC 14.2.0, Glibc 2.41, musl 1.2.5). No pre-built binaries — every toolchain
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is compiled from source on your hardware.
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**Silicon Identity.** Every binary produced by a BTC.sh toolchain includes
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an immutable ELF note (`.note.BTC`, note type NT_VERSION) and an extended
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filesystem attribute (`user.btc.stamp`) linking the binary to the specific
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hardware, toolchain version, and forge environment that created it.
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**Volatile Cleanroom.** All compilation occurs in a ramfs mount, ensuring zero
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I/O wear on host hardware and a pristine build environment on every invocation.
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**Thermal Sentinel.** Integrated telemetry loops prevent thermal runaway and
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memory saturation during heavy LTO (Link Time Optimization) phases.
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**Forensic Auditing.** Every build creates a verifiable manifest, enabling
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traceback of any binary to the exact source tree, configuration, and forge
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state that produced it.
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**Zero-Trust Deployment.** Mandatory AGPLv3 licensing protects the toolchain
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logic from proprietary SaaS capture.
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## Host Requirements
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- A standard Linux host (Debian, Arch, Fedora, Source Mage, etc.) with a
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working native GCC toolchain.
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- Root (EUID 0) is required for ramfs mounting and xattr stamping.
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- Sufficient RAM for the ramfs build environment (8 GB minimum recommended
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for x86_64 targets; 4 GB for embedded targets).
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- Persistent storage at `/opt/BTC` for logs, release archives, and cached
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source tarballs.
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## Licensing
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GNU Affero General Public License v3.0 (AGPL-3.0). Per Section 13, the forge
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includes an interactive notice at runtime. Network deployment of modified
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versions requires providing the Corresponding Source to your users.
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## Acknowledgments
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Original architecture based on scripts by Charles M. "Chip" Coldwell, Harvard
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University. Modern cross-compilation, hardening, and sovereignty features
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engineered by Jeremy Anderson dcos.net (2012–2026). |